***************** <!channel> Hello, We’ve identified an issue effect silicon testing for MPW-2 projects using Caravan (

user_analog_project_wrapper

). We found that there are two connections missing from the management area to IO[0] and IO[1]. This was affecting the Nucleo diagnostic test for these projects. The primary symptom is a user would get a “Winbond SRAM” error when trying to run the diagnostic. It also means these IO pads can not be used as outputs for the management SoC. The Nucleo software has been updated to work around this issue. The new version (1.2.0) has been pushed to the caravel_board repo. The README has been updated to explain how to run the diagnostic for analog projects (see ’make run_analog PART=<id>). Below is a link to the updated README… https://github.com/efabless/caravel_board/blob/main/firmware_vex/nucleo/README.pdf ******************

@jeffdi @Tim Edwards These 4 signals, right?

/gpio_control_bidir_1\[0\]/mgmt_gpio_oeb
/gpio_control_bidir_1\[0\]/mgmt_gpio_out
/gpio_control_bidir_1\[1\]/mgmt_gpio_oeb
/gpio_control_bidir_1\[1\]/mgmt_gpio_out

Yes, those are the ones. They should be pretty clear in a top level LVS.

I think they were disconnected in the verilog also, so LVS matches. I got those from the CVC results.

caravan.v

has had

jtag_out

,

jtag_outenb

and

sdo_out

,

sdo_outenb

that only connect to `gpio_control_block`s.

caravel.v

has

mgmt_io_out[0:1]

and

mgmt_io_oeb[0:1]

from

housekeeping

connected to the corresponding blocks. (edit: note this is on MPW-2. The current

caravan.v

does not use

jtag_out*

or

sdo_out*

.)

Okay. I guess it simplifies things if it just passes LVS. The error is known to have been fixed, so I'm not worrying about it too much other than noting how it affects Caravan projects for MPW-two. It's actually a relief to know that the MPW-two Caravan projects actually work; by not being able to talk to the housekeeping SPI, I had passed them off as untestable for a long time, until Jeff proved that they were able to run a program if it was already in the SPI flash, and I found out that the Nucleo hat was set up in a way that let the Nucleo read the data coming back from the SPI flash directly, bypassing GPIO 1 (SDO).