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#mpw-2-silicon
Title
# mpw-2-silicon
g

gatecat

02/06/2023, 11:33 AM
I am experimenting with the housekeeping SPI interface. It seems like it might be slipping a bit. Using a PLL register control register as a random test register whose value doesn't matter but I can write back and read; the following mpy code:
Copy code
slave.write([CARAVEL_REG_WRITE, 0x0e, 0x55])
    print("pll readback: {:04x}".format(int.from_bytes(slave.exchange([CARAVEL_STREAM_READ, 0x0e], 1), 'big')))

    slave.write([CARAVEL_REG_WRITE, 0x0e, 0xAA])
    print("pll readback: {:04x}".format(int.from_bytes(slave.exchange([CARAVEL_STREAM_READ, 0x0e], 1), 'big')))
prints
Copy code
pll readback: 00ab
pll readback: 0054
if I use
CARAVEL_STREAM_WRITE
instead of
CARAVEL_REG_WRITE
, then the writes are totally ignored
tried another chip just in case it was a particular failure with one but seeing the same behaviour...
t

Tim Edwards

02/06/2023, 1:58 PM
Yes, the housekeeping SPI on MPW-two was synthesized without the tools being told that the SPI SCK line was a clock driver for the whole thing, so basically it got no internal timing analysis, and the truly surprising thing is that it works at all. Writing registers through the SPI is definitely an issue for most of the registers. The primary issue is a hold violation in the serial chain (sounds familiar. . .) that loads the 8-bit input register from incoming SPI data. That causes bits to slip, as you noted. I have not analyzed it thoroughly, but it looks like whatever you write to a single byte, the next-to-last bit gets duplicated in position 0. That makes it impossible to program the last two bits to
01
or
10
. That disables several things on-chip including the ability to run the digital locked-loop (although it can be either disabled or run in DCO mode). One way to get around this makes use of the fact that the housekeeping registers have two accesses, one through the SPI and one through wishbone. So most of the registers can be programmed through compiled C code running on the SPI flash. But. . . there was another error where a portion of the registers (including the DLL controls) are in an address range that was not decoded by the processor, and so can't be reached through the wishbone bus.
👍 1
g

gatecat

02/06/2023, 2:00 PM
okay, thanks! it seems like that's actually unrelated to the problems entering SPI flash bypass mode, which I'll try and investigate now
I was not so interesting in the housekeeping SPI other than to try and debug whether the SPI was responding at all
t

Tim Edwards

02/06/2023, 2:04 PM
Yes, I figured that, but I don't think the timing issue in the housekeeping SPI interface has been mentioned before, and certainly not explained in detail. I will try to get a list of known issues posted soon.