Stefan Schippers
02/03/2023, 5:12 PMTim Edwards
02/03/2023, 5:54 PMBarak Hoffer
02/06/2023, 8:56 AMStefan Schippers
03/13/2023, 10:56 PM** sch_path: /home/schippes/.xschem/xschem_library/xschem_sky130/sky130_tests/tb_reram.sch
N1 TOP 0 nFilament sky130_fd_pr_reram__reram_model
V1 TOP 0 PWL (0 0 1u 1.8 2u 0 3u -1.8 4.0u 0.0)
.save i(v1)
**** begin user architecture code
.ic v(nFilament)=3.8
.control
* Modify according to your specific location
pre_osdi /mnt/sda7/sky130_fd_pr_reram_git/cells/reram_cell/sky130_fd_pr_reram__reram_cell.osdi
save all
tran 0.1n 4.0u
write tb_reram.raw
.endc
** opencircuitdesign pdks install
* .lib /home/schippes/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
This is the error:
doAnalyses: TRAN: Timestep too small; time = 9.29228e-07, timestep = 1.25e-22: trouble with node "nfilament"
tran simulation(s) aborted
Tim Edwards
03/14/2023, 2:32 AMBarak Hoffer
03/14/2023, 7:55 AMStefan Schippers
03/14/2023, 8:59 AMN1 TE BE sky130_fd_pr_reram__reram_model nFilament=3.8
Because using an additional pin and controlling via .IC yields a circuit with a (theoretically) undefined voltage node as the nFilament pin is floating. Simulators may resolve this by using some tricks, but this often worsens convergence of the whole circuit.Barak Hoffer
04/12/2023, 9:16 AMStefan Schippers
04/13/2023, 7:36 AM