I have seen that ngspice has very recently switched from ADMS to OSDI (OpenVAF) verilog-A support. This allows to easily build verilog-A models (example: reram) and simulate without doing magic things like rebuilding ngspice. Has anyone had a chance to look at this? in the coming days I want to update the xschem reram model according to this change.(cc @Talha Bin Azmat @Tim Edwards) If someone has already done some investigation please let me know. I have already built ngspice-39 and downloaded the openvaf compiler so i am ready to go...

I attended the webinar from the OpenVAF developer that undoubtedly precipitated this change (Holger Vogt was on the same call). But no, I haven't done any work with OpenVAF modeling. I certainly welcome the ability to add device models to ngspice without recompiling the whole thing!

I tried to do a small POC in colab See the I-V curve - for some reason it doesn't capture the switching behavior (compared to a xyce simulation for example).

@Barak Hoffer I updated the sky130 reram repo, applied your patch, compiled with openvaf (same version as yours) but I get convergence issues. I see the reram model is now a 3 terminal device. The netlist seems very similar to yours, but can't simulate it.

** sch_path: /home/schippes/.xschem/xschem_library/xschem_sky130/sky130_tests/tb_reram.sch
N1 TOP 0 nFilament sky130_fd_pr_reram__reram_model
V1 TOP 0 PWL (0 0 1u 1.8 2u 0 3u -1.8 4.0u 0.0)
.save i(v1)
**** begin user architecture code


.ic v(nFilament)=3.8
.control
  * Modify according to your specific location
  pre_osdi /mnt/sda7/sky130_fd_pr_reram_git/cells/reram_cell/sky130_fd_pr_reram__reram_cell.osdi
  save all
  tran 0.1n 4.0u
  write tb_reram.raw
.endc

** opencircuitdesign pdks install
* .lib /home/schippes/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt

This is the error:

doAnalyses: TRAN:  Timestep too small; time = 9.29228e-07, timestep = 1.25e-22: trouble with node "nfilament"
tran simulation(s) aborted

Three terminal??

Yes there might be convergence issues, can you share your model definition? You can improve convergence by changing the smoothing and Kclip parameters. The third terminal is actually a state variable for the filament state, and it is exposed as a terminal so you can control its initial state using the ic command.

@Barak Hoffer (cc @Tim Edwards ) Is the third terminal controlling some threshold or internal state of the model? Changing pins in existing devices must be a last resort as it breaks existing designs. I also think LVS netlists must only have "physical" pins, this is not a problem, i can do that. Just wondering if this is the correct strategy.

I have updated my repo:https://github.com/barakhoffer/sky130_ngspice_reram Now the reram cell is inside a sub circuit, and the nFilament node is internal and the initial condition can be supplied as a parameter

Hi, @Barak Hoffer I will go through the reram symbol and testbench and make the required updates. Good the state variable is now internal, as the external pin was a bit problematic, expecially since it changes the interface of the previous symbol. Thanks!