Hi, I'm confused about setting up the parasitics extraction for a flattened layout made out of imported custom cells. The following image in the attachment shows my current test setup for the top circuit, schematic of the top circuit symbol, unflat layout, and flat layout. The top circuit is DRC and LVS clean. I am able to perform a post layout simulation without the parasitics included. However the simulation does not have the expected output when I tried to include the parasitics. I followed this sequence of command:

flatten cellname_flat
load cellname_flat
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice

I would like to make sure I'm not setting things up incorrectly for parasitics extraction through magic.

I see the

EESPFAL_s0_flat

block is driving the the same oitputs as the hierarchic schematic. If you place the layout extracted circuit into your testbench you should use different outputs, otherwise there is contention on nets

s0

and

s0_bar

The set of extraction commands looks generally correct. Magic should be maintaining the port order of the subcircuit ports after flattening, but check to make sure that the port order hasn't changed.

Thank you for pointing those out and I have made changes to reflect that. I totally forgot about the port order changing. Currently I have another issue when I ran extresist where I'm having "Bad device location", "Couldn't find device", and "Error in extracting node". The current flat.spice file only has parasitic capacitance. I have included a section of the error message in the attachment. Should the proper way to run extresist for this hierarchic layout is to individually generate its .sim files?