Hi all. I am facing a problem in my design synthesis. I am trying to synthesize a code but am facing a problem when synthesizing. The tools used are Openlane and technology node is GF180 nm. The issue is that when synthesizing verilog blocks such as following are not completely synthesized and only partially synthesized. e.g. "//a is a single bit value with value 0 or 1 //f is a 8 bit vector and fin is a 16 bit vector //depending on the value of a, either the first half or the second half of the fin goes to f code is as //follows case (a) 0:begin f=fin[7:0]; end 1:begin f=fin[15:8]; end" The problem is that after the net-list is generated only the first half of the fin is connected and the rest of fin is removed i.e. only the condition for 1st case block is synthesized rest is removed (in optimization pass I presume). I have confirmed this from the netlist as well as gds generated where the pins for fin[15:8] are unconnected. I have tried to create illusions in the code by creating a dummy register and connecting the unused part of input fin to that register but to no avail. The net-list still does not connect the upper parts of fin to anything. The above sample code is part of a larger code block and there are more case and if statements on top of this block. I am expecting a chain of multiplexers to be used to synthesize the logic. I am hoping if anyone can tell what kind of coding style can be opted to avoid this problem?? How can this logic be written so that this issue does not arise for other designs. Regards Abdul Moiz

This doesn't seem like enough information to say much. You are probably better off asking in the yosyshq slack area as this is a yosys question

got it 👍