set the channel description: To review designs

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What kind of designs may be reviewed here ? Does RTL design for Communication protocols count ?

Anything's ok, I believe. I personally can probably only give feedback about the layout, but other people can probably help with other areas.

@User Was hoping to pick your brain about some layout issues with my design. There's quite a few macros which I am manually placing. I am placing them towards the edges, but leaving enough space for the met4/met5 straps to provide power to the chunks of met1 between the edge and the macro. I did this because I can't see anything to prevent placement from putting a cell in these regions (eg buffering an I/O) and as such they'd be unpowered. I was wondering what best practices are here. I can move them closer to the edges, but I presume I still need some space to route the user_project_wrapper external I/Os. My macro pin placement avoids these narrow areas, so that isn't a problem. How do I avoid the original placement issue in that case? Does Openlane need an easy way to specify placement blockages?

@User: @User and me are wondering if there is a way to do a v2lvs with netgen?

Hi! 1. What are the typical use cases for utilizing APB over AHB and vice versa? 2. What determines selection of AXI over APB/AHB? Is it just operating frequency or are there some other parameters? At what frequency does we use APB, then AHB and then AXI? 3. Why do we use bridges and not use AXI all over with some modifications like using AXI-Lite where required? I have gone through their specs but haven't really found satisfactory answers to the above or, I could have missed them. Would really help if someone answers it here! Thanks, in advance!

@User Hey Mitch, I am working with @User on some designs. We are using the OpenFASOC flow for gds generation. When we tried simulating the pex netlist generated by magic, the netlist had incorrect power/ground/bulk connections. Do you know how to resolve this? Thanks For example, on line 180-181, the VPWR VGND VNB and VPB are not connected correctly.

@User @User I just realised I had a clock constraint on the UART RX line. That, together with a high clock tree delay results in loads of delay buffers on the UART RX input, which seems silly. Is it ok to leave the pin unconstrained? It is after all asynchronous, so we shouldn't care about the signal lining up with the clock. Can I leave the TX line unconstrained too?

I don't know much about caravel but if it is truly asynchronous then that seems fine. @User in case you have any further comments on asynch signals in sta.

I don't think it's good to leave the signal completely unconstrained. There must be some required relationship between the individual bit lines. A multicycle path with a different setup and hold multiplier to bound what is allowed without overconstraining should work for you.

I am having a LVS failure with two unmatched pin around power .. Any suggestion how to fix this File: 26-user_project_wrapper.lvs.lef.log LVS reports: net count difference = 0 device count difference = 0 unmatched nets = 0 unmatched devices = 0 unmatched pins = 2 property failures = 0 Total errors = 2 File : 26-user_project_wrapper.lef.log shows below error saying Power pins are different .. Subcircuit pins: Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper -------------------------------------------|------------------------------------------- vssd1_uq9 |vssd1 Mismatch vccd1_uq26 |vccd1 Mismatch In GDS review wise: Power hook looks to good from Core Ring to Hard Macro

Hi, 1. Does anybody know how to verify my ESD protection design? 2. Is there any documentation available on how to make a GPIO test chip?

@User @User I'm trying to resolve hold violations I see when doing hierarchical STA on my entire design. All openlane runs including the top level integration pass STA without any hold violations, the issue is the interface between the top level and the macros.

Hi folks, I understand, that in this channel users can propose their project to be reviewed by others, right ? I would love to have some killing issues cleaned before deadline. Anyone interested in reviewing my project (only GDS submitted so far), which passes tapeout check on the efabless site. https://github.com/cloudxcc/WaveSync_7.git For instance, is the power connection of the macros I used (SRAM and custom) okay ? I would be happy to treat reviewers for lunch if we meet at any of the OrConf etc. conferences !!! In any case, as always, thank you in advance. Cheers, Tobias

Hi all. I am facing a problem in my design synthesis. I am trying to synthesize a code but am facing a problem when synthesizing. The tools used are Openlane and technology node is GF180 nm. The issue is that when synthesizing verilog blocks such as following are not completely synthesized and only partially synthesized. e.g. "//a is a single bit value with value 0 or 1 //f is a 8 bit vector and fin is a 16 bit vector //depending on the value of a, either the first half or the second half of the fin goes to f code is as //follows case (a) 0:begin f=fin[7:0]; end 1:begin f=fin[15:8]; end" The problem is that after the net-list is generated only the first half of the fin is connected and the rest of fin is removed i.e. only the condition for 1st case block is synthesized rest is removed (in optimization pass I presume). I have confirmed this from the netlist as well as gds generated where the pins for fin[15:8] are unconnected. I have tried to create illusions in the code by creating a dummy register and connecting the unused part of input fin to that register but to no avail. The net-list still does not connect the upper parts of fin to anything. The above sample code is part of a larger code block and there are more case and if statements on top of this block. I am expecting a chain of multiplexers to be used to synthesize the logic. I am hoping if anyone can tell what kind of coding style can be opted to avoid this problem?? How can this logic be written so that this issue does not arise for other designs. Regards Abdul Moiz

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