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Hi All, how much is the cycle time (in ns) or in number of cycles , the latency from riscv core to the user project area (our design) - is it mentioned somewhere or how to calculate ? Thanks

Hi Ryan, good question. I don't know the answer but I would think you can get it from the top level timing analysis. You can run that with these instruction: <https://caravel-user-project.readthedocs.io/en/latest/#running-timing-analysis-on-existing-projects>

Then there will be a lot of timing files generated, I suppose you'd choose a typical corner for your question?

Then you'd want to find a timing path that goes from the gpio to your design and that should tell you want you want to know

I'm interested to know the answer myself, so let me know if you try it