@Matt Venn: Having looked more thoroughly into the issues with the MPW-two chips, I have tentatively identified three major issues: (1) The software that the system is putting into the C code for a program to configure the GPIO through bit bang is not working correctly. I ran a test where I converted the bit-bang bitstreams into constant configuration values that I could plug into the C program and then run the automatic transfer instead of the bit-bang code, and I get a different response from the chip. In particular, channel 0 behaves differently, and it is difficult to screw up the configuration of channel 0 because it has no hold violations going into it. I can share the code I wrote that converts the bit-bang bitstreams into constant values, if you like. It's helpful for debugging. (2) I have proven to my satisfaction that the distribution of dependent and independent hold violations changes when you take the caravel development board off of the Nucleo board and run it independently. There are presumably small temperature and/or voltage differences that affect the timing of hold violations. So we need to set up a way to run user programs while the board is still connected to the Nucleo board where it was calibrated. (3) I think there is a general misunderstanding of the limitations of setting the GPIO configuration. The most obvious problem is that the independent hold violations cause bits to slip from the highest bit of one channel (the digital mode, affecting how it's configured for input or output) to the first bit of the next channel (the management enable/disable bit). Since the standard mode for output is

110

, if there is an independent hold violation between that and the next channel, then the next channel will always get the management enable bit set to

1

no matter what. That means that if there are two contiguous GPIOs that both need to be set as user-controlled outputs, one of them can't use the

110

mode. The only work-around in that case is to substitute the mode

011

. That is a weak pull-down mode. The GPIO can still act as an output, but when it tries to drive the output to 0, it does so through a 5kOhm resistor, and so that will limit the speed of the system. There is no way to get around this limitation if you have two user outputs side by side and they both have to be active and there's an independent hold violation between them. Also: The software that we have isn't very clever and so sets the output mode to

011

(slow pull-down) for all outputs, regardless of what's in the next channel. So the software is not necessarily giving you the best possible configuration.

@Tim Edwards I am not clear on what it mean by H_DEPENDENT Hold violation. I assume H_INDEPENDENT -> Means there is one bit slip between two GPIO 13 bit Shift chain. Are we expecting hold violation with-in 13 bit shift chain inside the each GPIO ? My understanding was we have hold violation only between GPIO chain ?

There are no hold violations inside a GPIO control block, only between them. Your understanding of an independent hold violation is correct. The dependent hold violation has a one-bit slip when there is a 1->0 transition and does not have a slip otherwise. The effect of this is different than an independent hold violation (which has a one-bit slip on both a 1->0 transition and a 0->1 transition). The dependent hold violation acts like this: Whenever you shift a series of "1" bits through the point where the hold violation occurs, the last "1" bit in the series gets converted to a zero. So if you push the value "0111000" through a dependent hold violation, it becomes "0110000" on the other side. To make sure you get the right value through to the end of the serial chain, you need to keep lengthening runs of "1" for each dependent hold violation that the data passes through. If you have too many dependent hold violations then you run out of consecutive zeros and the correct value can't get to the destination.

Thanks @Tim Edwards for the detailed explanation. I see fixing Dependent violation is more complicated than Independent hold violation, adding to this both the serial chain shifted by same clock creating additional algorithm complexity.