@Mihai Hurdugaciu I need to know the actual steps you are following to reproduce the error. As an example it seems like the OpenLane does not know about

.vh

files at all, because you didn’t mention the “include” folder. And there might be some other issues like this.

Hi , For Openlane i run :

. /flow.tcl -interactive
% package require openlane 0.9
% prep -design controller -tag RUN_2023.01.25_09.43.04 -overwrite
% run_synthesis

I had also the use case when in the /src folder I had just

vsdmemsoc.v, rvmyth.v, clk_gate, rvmyth_gen.v

but I got the error that

.vh

file is missing . The

.vh

files are link from my understanding from

include

used in verilog file. Additional I do not use an include folder because I saw here something about not supporting this. https://openlane.readthedocs.io/en/latest/usage/chip_integration.html

You are referencing Verilog files by

"VERILOG_FILES": "dir::src/*.v"

but I think you also need to add

"VERILOG_INCLUDE_DIRS": "dir::src"

if you put all

.v

and

.vh

files in

dir::src

directory. For more info please take a look at the following link: https://github.com/manili/vsdmemsoc_mpw3/blob/4a9859d60fed5eb33fddc2e32b0f016d11bb6834/openlane/user_proj_example/config.tcl Specifically L28. I don’t know what do they actually mean by the following statement in the link:

* The `include directive is not supported.

but I’m pretty much sure that you need the `include syntax to be able to synthesize your design and the

VERILOG_INCLUDE_DIRS

option is actually part of the OpenLane’s configuration for synthesis (check the link). Maybe @Vijayan Krishnan have some ideas about this statement?

I included the inlcude directory the same error, you can see : OpenLane commands, config.json, folder structure and synthesis.log.

@Mihai Hurdugaciu Please switch line 3 & 4 in json file. First read include directory then source verilog files. Share me error log and source file to try at out end

Done, sane error, maybe next days I will try with

config.tcl

variant. But I saw in the documentation that

.json

is preferred.

{
  "DESIGN_NAME": "vsdmemsoc",
  "VERILOG_INCLUDE_DIRS": "dir::src/include",
  "VERILOG_FILES": "dir::src/*.v",
  "CLOCK_PORT": "CLK",
  "CLOCK_PERIOD": 10,
  "EXTRA_LIBS": "dir::src/libs/*.lib",
  "DESIGN_IS_CORE": true
}

please file issue here: https://github.com/The-OpenROAD-Project/OpenLane/issues with results you got and what is the expected one

Hi , now I used

VERILOG_FILES_BLACKBOX": "dir::src/include/sram_32_256_sky130A.v"

variable and I got a relevant report. Thnaks