Hello, I have the following issue: • I am learning the OpenLane flow • I am trying to setup Open lane for VSDMemSoC example design https://github.com/MihaiHMO/VSDhdp/tree/main/VSDMemSoC • I copy all

.v, .vh , .lib , .lef

files from git module and include folders -> into the

Openlane/design/src

folder • I am stuck at the synthesis stage Here you can see the basic `config.json`:

{
  "DESIGN_NAME": "vsdmemsoc",
  "VERILOG_FILES": "dir::src/*.v",
  "CLOCK_PORT": "CLK",
  "CLOCK_PERIOD": 10,
  "DESIGN_IS_CORE": true
}

The error :

Executing Verilog-2005 frontend: /openlane/designs/vsdmemsoc/src/rvmyth_gen.v
/openlane/designs/vsdmemsoc/src/rvmyth_gen.v:12: ERROR: syntax error, unexpected TOK_GENVAR

Additional, if I run the following yosis script the synthesis is working :

read_verilog -I./include ./module/vsdmemsoc.v
read_verilog -I./include ./module/controller.v
read_verilog -I./include ./module/clk_gate.v
read_verilog -I./include ./output/compiled_tlv/rvmyth.v
read_liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty -lib ./lib/sram_32_256_sky130A_TT_1p8V_25C.lib
synth -top vsdmemsoc
dfflibmap -liberty ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
opt
abc -liberty ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib -script +strash;scorr;ifraig;retime;{D};strash;dch,-f;map,-M,1,{D}
flatten
setundef -zero
clean -purge
rename -enumerate
stat
write_verilog -noattr output/synth/vsdmemsoc.synth.v

Thanks.

@manili - i think you had solved this issue in past