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# klayout
a
Could you please send a screenshot?
z
IMG_20230124_173032.jpg
a
@z-a-p-k-i-n-g Did you create a CDL netlist for your design?
You need to provide that in the commandline
z
Yea I did provide the .spice file
I created that using xschem
a
Topcell name are not the same
You need to make sure that they are the same
z
U mean like renaming inv.spice to inverter.spice?
a
No
The subcircuit name inside the file
What was commandline you used?
z
IMG_20230124_173945.jpg
a
That seems to be working for you
z
Its just an inverter
But lvs isn't matching
a
Are you sure the layout is the same?
z
Yea the old errors are gone
IMG_20230124_174350.jpg
a
Are you sure it should be clean?
z
Yea ig so...u can hav a look at my layout
It's not generating the .lyrb too ig
a
It will generate lvsdb
z
Sry my bad...yea that one is not being generated
a
Please open an issue on the efabless pr repo
And please send the files GDS and Netlist
z
Sure thanks for ur help
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