hi @Vijayan Krishnan , does the placement step by default flatten the design ?? i see the modules are flattened from synthesis verilog netlist to the placement netlist . If yes , anyway to block this ? Thanks,

Currently flow using flatten design only.

You can remove -flatten from the yosys scripts but you will likely get worse results as cross module optimizations will be blocked.

i removed from yosys , but the placement netlist seems flattened again - any idea ?