I've been wrapping up some stability testing for an op-amp I have designed. However, realized I need to complete the stability testing whilst including the capacitance associated with the analog pads. Might y'all know where I can find the value or model of the capacitance of the analog pad (Caravan)?

Hi Jon, I don't have the information for the Sky130 process but here are the values I typically use for the bond pad and ESD structures. The Bond Pad plus ESD structure is around 4pf. If you also want to include the capacitance of a Printed Ckt Board trace, I use 10pf per inch length of trace. Note that 1 inch is 2.54 cm. If your chip package is using Bond Wires and not the Solder Bumps, I will typically use 10nH for a Bond Wire inductance. The new "flip-chip", solder bump packages have low pin inductance and I typically don't include any inductance for the "flip chip", solder bump, packaging technology.

Thank you @Larry Harris for the information. I greatly appreciate it. @Tim 'mithro' Ansell might you have insights into the cap value associated with the analog pads?

I think @Tim Edwards can help you?

@Jon Ho: I designed the pad to have minimal capacitance; there is nothing under the pad except for an isolated deep nwell layer, and the capacitance from pad to deep nwell is 29fF (according to extraction from Magic). Pretty much all the capacitance is going to be in the packaging. The analog pad has no ESD structures at all---it was designed that way to minimize capacitance so that it could be used for high-speed circuits. That means you need to add some kind of ESD protection (or handle the part very, very carefully), but then you get to control how much capacitance that adds to the pad.

Thanks for the information @Tim Edwards. Greatly appreciated.