Hi all, I taped out a bandgap reference circuit in college and got to measure one silicon sample with @Eric Smith after I graduated. Ideally I would have more samples but nevertheless I want to share the data. Data is in a github here. Silicon data is shown in plots in the README. Raw data (csv) and scripts used to make plots are in

silicon_measurements/

The (limited) data shows a discrepancy between layout-extracted circuit simulation and measured silicon. The discrepancy is in the temperature coefficient of reference voltage output (see github: Output reference voltage vs. load and temperature and table: design goals vs. post-layout, extracted circuit performance). The discrepancy in temp co is 3.6 ppm (simulated) vs. 137.6 ppm (measured). Quite different. My initial approach would be to dig into the BJT circuit model and investigate what could have caused this large difference. Iterate over (relevant) BJT model parameters, modify each one, and observe how each change either moves or doesn’t move the tempco from 3.6 ppm to 137.6 ppm. I am curious to hear the channel’s thoughts on what could be the source of this performance mismatch. I’m hoping someone else has the time and interest to help find the answer. I think this could be a nice learning opportunity for myself but I just started graduate school and I fear I will forget about this question; sharing the question with you all helps me stay interested in answering it 🙂

I recall looking at the layout some time fairly recently and deciding that there were less-than-ideal routes and/or vias that would add a significant enough resistance to throw off the output. How did you get the post-layout extraction?

Less-than-ideal is putting it politely! This is the script I used for extraction: https://github.com/johnkustin/bandgapReferenceCircuit/blob/7f9bb8bf0318db0888ac9a0bc881b0f2f36ea06b/layout/pex.tcl