does anyone know, why it is the case, when I try to do an gate level simulation with the OpenLane Output Netlist, that every output signal becomes x? Ive seen that there are some open Issues on the github on that topic... if I let the normal pre netlist testbench run with the input file everything seems to be fine...

@Enno When you say gate level simulation with output netlist are you referring to the verilog gate level netlist or the extracted spice netlist?

I mean the verilog netlist <filename>.nl.v in the results folder

You’re including the standard cell verilog, right?

$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

of course... as well as the primitives.v... and iverilog takes everything without an error... Btw. do I need to power the netlist? I mean the .nl.v module has no power inputs, right?

@Enno Looks like you might need the powered version of the netlist. The primitive verilog includes a power check module and the output of this is ORed with the actual logic.

primitive sky130_fd_sc_hd__udp_pwrgood_pp$G (
    UDP_OUT,
    UDP_IN ,
    VGND
);

    output UDP_OUT;
    input  UDP_IN ;
    input  VGND   ;

    table
     // UDP_IN VPWR : UDP_OUT
          0     0   :    0     ;
          1     0   :    1     ;
          ?     1   :    x     ;
          ?     x   :    x     ;
    endtable
endprimitive

Standard cell inverter

module sky130_fd_sc_hd__inv (
    Y   ,
    A   ,
    VPWR,
    VGND,
    VPB ,
    VNB
);

    // Module ports
    output Y   ;
    input  A   ;
    input  VPWR;
    input  VGND;
    input  VPB ;
    input  VNB ;

    // Local signals
    wire not0_out_Y       ;
    wire pwrgood_pp0_out_Y;

    //                                 Name         Output             Other arguments
    not                                not0        (not0_out_Y       , A                     );
    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );

endmodule

So if there are no power connections, looks like you’ll get ‘x’ output. Do you have the powered netlist?

Yeah there is a powered Version but, it Always gives out errors while compiling... It is the <Filename>.v File....