GitHub
01/15/2023, 2:36 PMwrite_powered_verilog
where write_verilog
didn't read the def produced by write_powered_def
. write_powered_def
proved to be useful as it parses a yosys netlist where(supposedly) all power connections are defined. If due to a misconfiguration or other reasons, openroad creates faulty power connections, the openroad gl netlist will also have the same faulty power connections resulting in misleading lvs results. The mentioned behavior was surfaced in #1600
The-OpenROAD-Project/OpenLane
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01/18/2023, 4:06 AM