There was an earlier conversation about

Unconnected PDN node on net vdd at location (19.600um, 1524.880um), layer: 1

errors during "STEP 7" -- PDN. I'm trying to do sub-macros on GF180MCU, and while my SRAM works just fine, I put together a 2r1w macro for a register file as a sub-module and that's not working. The macro is rather wide at 180nm -- 500x1350, so I don't think I'm running up against an issue of having power rails too far away. I've added my module to

FP_PDN_MACRO_HOOKS

but

7-pdn.log

still complains "Supply pin vdd of instance minimax.regfile is not connected to any net." -- and it's then followed by "Inserting grid: macro - minimax.regfile". What is the proper way to insert a sub-module like this? And how can I connect the various PDN nodes?

Can you share your config file?

I've pushed it to https://github.com/xobs/caravel-minimax/tree/macro-separation -- the regfile macro is in

minimax_rf

and the actual topfile is in

mimi

.

Looking at the documentation here seems to indicate it should work, but what about trying

There are some shorthands for the exposed default variables:
dir:: is equivalent to ref::$DESIGN_DIR/
pdk_dir:: is equivalent to ref::$PDKPATH/      <- this one
scl_dir:: is equivalent to ref::$SCLPATH/

Also

PDKPATH

is probably

$PDK_ROOT/$PDK

so make sure you have both of those defined before running

flow.tcl

.

Which configuration should I adjust to get it to connect power pins? Or is there a special

PDN_CFG

I need to use in order to create my own macros?

I think your

FP_PDN_MACRO_HOOKS

needs

,

before

"

.

"FP_PDN_MACRO_HOOKS": [
            "bank1.ram1 vdd vss vdd vss,",
            "bank1.ram2 vdd vss vdd vss,",
            "bank1.ram3 vdd vss vdd vss,",
            "bank1.ram4 vdd vss vdd vss,",
            "bank2.ram1 vdd vss vdd vss,",
            "bank2.ram2 vdd vss vdd vss,",
            "bank2.ram3 vdd vss vdd vss,",
            "bank2.ram4 vdd vss vdd vss,",
            "bank3.ram1 vdd vss vdd vss,",
            "bank3.ram2 vdd vss vdd vss,",
            "bank3.ram3 vdd vss vdd vss,",
            "bank3.ram4 vdd vss vdd vss,",
            "bank4.ram1 vdd vss vdd vss,",
            "bank4.ram2 vdd vss vdd vss,",
            "bank4.ram3 vdd vss vdd vss,",
            "bank4.ram4 vdd vss vdd vss,",
            "minimax.regfile vdd vss vdd vss"
        ],

Oh, I thought that wasn't necessary due to the fact that it's a JSON array. If it's required, then I'll file a bug on that. Let me give it a shot.

Your

rtl/mimi.v

has

vdd

and

vss

defined at the top level

module mimi #(
    parameter PC_BITS = 10,
    parameter UC_BASE = 32'h0000200,
    parameter TRACE = `TRACE,
)(
`ifdef USE_POWER_PINS
    inout vdd,	// User area 1 1.8V supply
    inout vss,	// User area 1 digital ground
`endif

but the module instantiations don’t

gf180mcu_sram_512x32 bank2 (
        .clk(mem_clk),
        .reset(mem_reset),
        .en(ram_addr[12:11] == 2'h1),
        .addr(ram_addr[10:2]),
        .rdata(rdata_bank2),
        .wdata(wdata),
        .wen(wmask == 4'hf)
    );

    // Bytes 4098-6143
    wire [31:0] rdata_bank3;
    gf180mcu_sram_512x32 bank3 (
        .clk(mem_clk),
        .reset(mem_reset),
        .en(ram_addr[12:11] == 2'h2),
        .addr(ram_addr[10:2]),
        .rdata(rdata_bank3),
        .wdata(wdata),
        .wen(wmask == 4'hf)
    );
...

Can you try adding something like this?

gf180mcu_sram_512x32 bank2 (
`ifdef USE_POWER_PINS
    .vdd(vdd),	// User area 1 1.8V supply
    .vss(vss),	// User area 1 digital ground
`endif        .clk(mem_clk),
        .reset(mem_reset),
        .en(ram_addr[12:11] == 2'h1),
        .addr(ram_addr[10:2]),
        .rdata(rdata_bank2),
        .wdata(wdata),
        .wen(wmask == 4'hf)
    );

    // Bytes 4098-6143
    wire [31:0] rdata_bank3;
    gf180mcu_sram_512x32 bank3 (
`ifdef USE_POWER_PINS
    .vdd(vdd),	// User area 1 1.8V supply
    .vss(vss),	// User area 1 digital ground
`endif
        .clk(mem_clk),        .clk(mem_clk),
        .reset(mem_reset),
        .en(ram_addr[12:11] == 2'h2),
        .addr(ram_addr[10:2]),
        .rdata(rdata_bank3),
        .wdata(wdata),
        .wen(wmask == 4'hf)
    );

Apologies, I'd been working off of a branch. I've merged it to main. The branch has those signals already.