Filippo
01/08/2023, 11:09 AMflow.tcl all steps work correctly, except last (STEP 35 LVS). There are the power pin that are not connected. Why?
The verilog netlist is correct:Manuel M
01/08/2023, 12:23 PMpdn_cfg.tcl it seems OpenLane connects macros over met5-met4 by default. If you want connections met4-met1 to the macro then I'd try copying pdn_cfg.tcl to the design folder, set the new path "PDN_CFG": "dir::pdn_cfg.tcl", in config.json and add line add_pdn_connect -grid macro -layers "met1 met4" to pdn_cfg.tcl. If LVS passes, don't trust the result blindly, doublecheck the gds if everything is tied up correctly (the lower two power rails might never be connected due to distance rules, but technically GND always finds a connection over substrate)Filippo
01/08/2023, 1:53 PMFilippo
01/08/2023, 1:54 PMFilippo
01/08/2023, 2:05 PMVDD_NETS and VDD_NETS ?Manuel M
01/08/2023, 2:21 PMManuel M
01/08/2023, 2:23 PMVDD_NETS, definition which net connects to which port in FP_PDN_MACRO_HOOKSFilippo
01/08/2023, 2:29 PMlef write -hideFilippo
01/08/2023, 2:40 PMManuel M
01/08/2023, 3:06 PMlef with explicit port definition (pin layer in the lef), long enough to touch at least 2 rails of the vertical PDN. Don't know what -hide does to the obstruction layers between metal1 and metal4 btw. but there's a possibility this might prevent a connection down to metal1 rails.
Suggestion: The "cleanest" solution (since you are hardening a macro inside a macro) might be to restrict the PLL macro to use only layers up to metal3 (if possible) and then add VDD and GND power rails going horizontally all over the macro on metal3 with explicit port definition. Documentation on power grid control: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/usage/advanced_power_grid_control.mdManuel M
01/08/2023, 3:44 PMFilippo
01/09/2023, 10:19 AM