I try to harden an analog IP macro with digital pa...
# openlane
f
I try to harden an analog IP macro with digital parts. Using
flow.tcl
all steps work correctly, except last (STEP 35 LVS). There are the power pin that are not connected. Why? The verilog netlist is correct:
🌍 1
m
Looking at
pdn_cfg.tcl
it seems OpenLane connects macros over
met5
-
met4
by default. If you want connections
met4
-
met1
to the macro then I'd try copying
pdn_cfg.tcl
to the design folder, set the new path
"PDN_CFG": "dir::pdn_cfg.tcl",
in
config.json
and add line
add_pdn_connect -grid macro -layers "met1 met4"
to
pdn_cfg.tcl
. If LVS passes, don't trust the result blindly, doublecheck the
gds
if everything is tied up correctly (the lower two power rails might never be connected due to distance rules, but technically GND always finds a connection over substrate)
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f
@User, I try this solution but VDD and GND are not connected ...
Schermata 2023-01-08 alle 14.53.26.png,config.json,pdn_cfg.tcl
The name of my vdd and gnd port must be added to
VDD_NETS
and
VDD_NETS
?
m
What about the upper two rails not shown in the screenshot? They should be connected at least
nets pf the PDN in
VDD_NETS
, definition which net connects to which port in
FP_PDN_MACRO_HOOKS
f
No, the upper two rails are not connected because the VDD and GND port in lef file are on the left. I change it with
lef write -hide
If I use lef write instead, the error is this
m
I see, do you want them to be on the left? Because, power is just not connected the same way as signals. Power with the intention to connect to the vertical metal4-PDN will need horizontal rails in the
lef
with explicit
port
definition (pin layer in the lef), long enough to touch at least 2 rails of the vertical PDN. Don't know what
-hide
does to the obstruction layers between metal1 and metal4 btw. but there's a possibility this might prevent a connection down to metal1 rails. Suggestion: The "cleanest" solution (since you are hardening a macro inside a macro) might be to restrict the PLL macro to use only layers up to metal3 (if possible) and then add
VDD
and
GND
power rails going horizontally all over the macro on metal3 with explicit
port
definition. Documentation on power grid control: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/usage/advanced_power_grid_control.md
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For example what power distribution looks like in my own mixed-sig design, I have added vertical VDD and GND power rails left and right of this analog macro. The PDN on metal5 (yellow, horizontal) overlaps them in every circumstance and connects the macro to the power grid of the core
f
Thank you very much for your detailed explanation. I change my layout and now flow complete succesfully!
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