Check out Dinesh Annaya's @Dinesh A RISCduino design that uses a hierarachical design methodology and other interesting design concepts to achieve good PPA and timing closure using OpenROAD and OpenLane. https://theopenroadproject.org/implementation-of-riscduino-core-using-a-hierarchical-design-flow/

@Dinesh A Awesome work! I understand that in OL\OR you can only have one balanced clock tree per module. Unless this hasn’t changed\will change, a submodule per clock is a fair assessment. Sorry for my question, as the link refers to a page which is not a research paper, but it would be awesome to have a performance comparison when you follow a “single-module-per-clock-domain strategy” as an alternative. Don’t you think that the performance will improve? Cheers, Tobias PS: It also seems that you do not prefer logic on the user top level (aka user_project_example). Is that right? (I know it is tough on the wrapper level.)