#1600 Verilog `generate` does not preserve power connections Issue created by mole99 Description When instantiating multiple macros via the Verilog

generate

statement the power connections are lost somewhere in the flow and thus the macros are not connected to power. I had a look at the resulting file

tmp/signoff/25-user_project_wrapper.pnl.v

. The macro I had instantiated normally is connected to `vccd1`/`vssd1`, the other four instances via the

generate

statement are not connected to `vccd1`/`vssd1`. Example code snippet:

generate
    genvar i;

    for (i = 0; i < NUM_INSTANCES; i++) begin : memory

        sky130_sram_2kbyte_1rw1r_32x512_8 sram (
            `ifdef USE_POWER_PINS
            .vccd1(vccd1),  // User area 1 1.8V power
            .vssd1(vssd1),  // User area 1 digital ground
            `endif
            // Port 0: RW
            .clk0  (wb_clk_i),
            .csb0  (la_data_in[0]),
            .web0  (la_data_in[1]),
            .wmask0(la_data_in[5:2]),
            .addr0 (la_data_in[14:6]),
            .din0  (la_data_in[46:15]),
            .dout0 (select_dout0[i*DATA_WIDTH+:DATA_WIDTH]),
            // Port 1: R
            .clk1 (wb_clk_i),
            .csb1 (la_data_in[47]),
            .addr1(la_data_in[79:48]),
            .dout1(select_dout1[i*DATA_WIDTH+:DATA_WIDTH])
        );
        
    end
endgenerate

Expected Behavior The macros should be connected to power. Environment report

$ python3 ./env.py issue-survey
Kernel: Linux v6.0.0-6-amd64
Distribution: debian 
Python: v3.10.9 (OK)
Container Engine: docker v20.10.21+dfsg1 (OK)
OpenLane Git Version: cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: MISMATCH
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
---
Git Log (Last 3 Commits)

cb59d1f 2022-11-18T18:42:38+02:00 fix return values in `equally_spaced_sequence` (#1503) - Kareem Farid -  (grafted, HEAD, tag: 2022.11.19)
---
Git Remotes

origin	<https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin	<https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material No reproducible was packaged because the flow did not fail. I created a repository, ol-generate-bug, based on

caravel_user_project

to easily reproduce the issue. Please note that I installed

sky130A

next to the project folder under

dependencies/pdks

, so that the sram can be found. After

OPENLANE_ROOT

,

PDK_ROOT

and

PDK

are exported, you can run the flow via

make user_project_wrapper

. Relevant log output ``` $ make user_project_wrapper make -C openlane user_project_wrapper make[1]: Verzeichnis „/home/leo/Dokumente/workspace_test/caravel_user_project/openlane“ wird betreten # user_project_wrapper mkdir -p ./user_project_wrapper/runs/23_01_01_12_33 rm -rf ./user_project_wrapper/runs/user_project_wrapper ln -s $(realpath ./user_project_wrapper/runs/23_01_01_12_33) ./user_project_wrapper/runs/user_project_wrapper docker run -it -v $(realpath /home/leo/Dokumente/workspace_test/caravel_user_project/..):$(realpath /home/leo/Dokumente/workspace_test/caravel_user_project/..) -v /home/leo/Dokumente/workspace_test/dependencies/pdks:/home/leo/Dokumente/workspace_test/dependencies/pdks -v /home/leo/Dokumente/workspace_test/caravel_user_project/caravel:/home/leo/Dokumente/workspace_test/caravel_user_project/caravel -v /home/leo/Dokumente/workspace_test/dependencies/openlane_src:/openlane -v /home/leo/Dokumente/workspace_test/caravel_user_project/mgmt_core_wrapper:/home/leo/Dokumente/workspace_test/caravel_user_project/mgmt_core_wrapper -e PDK_ROOT=/home/leo/Dokumente/workspace_test/dependencies/pdks -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/leo/Dokumente/workspace_test/caravel_user_project/caravel -e OPENLANE_RUN_TAG=23_01_01_12_33 -e MCW_ROOT=/home/leo/Dokumente/workspace_test/caravel_user_project/mgmt_core_wrapper -u 1000:1000 \ efabless/openlane:2022.11.19 sh -c "flow.tcl -design $(realpath ./user_project_wrapper) -save_path $(realpath ..) -save -tag 23_01_01_12_33 -overwrite -ignore_mismatches" OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c) This may introduce some issues. You may want to re-install the PDK by invoking

make pdk

. [INFO]: Using configuration in '../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/config.json'... [INFO]: PDK Root: /home/leo/Dokumente/workspace_test/dependencies/pdks [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33 [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [STEP 1] [INFO]: Running Synthesis (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/synthesis/1-synthesis.log)... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/synthesis/2-sta.log)... [INFO]: Creating a netlist with power/ground pins. [STEP 3] [INFO]: Running Initial Floorplanning (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/floorplan/3-initial_fp.log)... [INFO]: Floorplanned with width 2908.58 and height 3497.92. [STEP 4] [INFO]: Running IO Placement... [INFO]: Applying DEF template... [STEP 5] [INFO]: Performing Manual Macro Placement (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/placement/5-macro_placement.log)... [INFO]: Power planning with power {vccd1 vccd2 vdda1 vdda2} and ground {vssd1 vssd2 vssa1 vssa2}... [STEP 6] [INFO]: Generating PDN (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/floorplan/6-pdn.log)... [STEP 7] [INFO]: Performing Random Global Placement (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/placement/7-global.log)... [INFO]: Skipping Placement Resizer Design Optimizations. [STEP 8] [INFO]: Running Detailed Placement (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/placement/8-detailed.log)... [INFO]: Skipping Placement Resizer Timing Optimizations. [STEP 9] [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/routing/9-resizer.log)... [STEP 10] [INFO]: Running Detailed Placement (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/routing/10-diode_legalization.log)... [STEP 11] [INFO]: Running Global Routing (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/23_01_01_12_33/logs/routing/11-global.log)... [STEP 12] [INFO]: Writing Verilog (log: ../home/leo/Dokumente/workspace_test/caravel_user_project/openlane/user_project_wrapper/runs/… The-OpenROAD-Project/OpenLane