Hi, I am running the caravel precheck and it fails...
# openlane
e
Hi, I am running the caravel precheck and it fails in the XOR check. Does anyone know how to fix it?
r
there is probably a wire outside the allowed area
look at the gds file in magic - the parts outside the allowed area will be shown and you just need to delete them
e
Thanks for your help, i have the next questions. 1- why if i use the specific die are OpenLANE generate wires outside of that area? 2-i don't know how to use magic, i usually open the gds with klayout. could you have the command line to open the GDS with magic?. i tried open magic ans with GUI click on file/Read GDS. The following message apears Don't know how to read GDS-II: Nothing in "cifinput" section of tech file.
m
image.png
there is something very wrong with your power ring and pin positions
e
Thanks, i'll compare my config file with the default user_project_wrapper config file.
m
To open with magic, use
magic -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
a
Hi, I have also faced the same issue in this project, There is routing wires outside the pin locations. Mt config was the same as default except maybe elaborate only turned to 0 and fill insertion to 1. I was building directly in wrapper not by macro insertion.
e
Hi, So do you use "SYNTH_ELABORATE_ONLY ":0, and "RUN_FILL_INSERTION":1?
a
yep
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