Hi @Tim Edwards, my last thread was more about a small example design and some fooling around with edges. I thought I share some findings regarding the hold-time challenge on the WB\LA bus using larger designs as well. The insertion delay of a soc register, which shows up in the relevant min timing reports is ~4.05. The insertion delay of small user designs (like the default counter example) is roughly the same. So smaller designs are relatively safe w.r.t hold- time issues. Though I would have expected a lower bound as well. I created a larger design which spans almost the complete user area and has 64k registers. The notable insertion delay here is 9.50 ns. That’s a 5.5 ns difference. I get hold time violations on the LA interface of 0.17 ns. It is great to have a top-level STA, otherwise this kind of violation would have gone unnoticed. I realized that in this larger design, 10 delay-metal-cells are inserted per MGMT->USER signal. To be honest, I didn’t expect the tool flow to accomplish such a rather drastic optimization. But it seems to work, although there is still a violation right now. Also almost accurate, just 0.17 ns off. Congrats! Nevertheless, the delay cell insertion is huge for larger designs, (although relatively small compared to the design itself). These are ~40*10 for WB and 128*10 for LA-IN bus signals. I tried the solution to place an inverter in the WB_CLK tree in the large design (like the thread above). It resulted in no hold time violation and no delay cell insertion. Maybe a reasonable alternative for medium and large designs. I have updated my app note accordingly. https://github.com/cloudxcc/CaravelAppNotes/tree/main/AN_WBHT Cheers, Tobias