1. Executing Verilog-2005 frontend: /home/mukul/Desktop/design1/jubilant-funicular/caravel/verilog/rtl/defines.v ERROR: Can't open input file `/home/mukul/Desktop/design1/jubilant-funicular/openlane/MBA_module/runs/22_12_30_04_04/../../verilog/rtl/MBA_module.v' for reading: No such file or directory child process exited abnormally

Where is

MBA_module.v

located? Looks like it might be a bad path in your config file.

It's path is correct and still showing an error. project/verilog/RTL/MBA_module.v

So project is

MBA_module

, right? The directory you listed above is

RTL

where the directory with the error is

rtl

. Some OSs differentiate between upper and lower case and some don’t. If you’re running in docker, it may be different from your desktop.

It's in small case only rtl

Can you post your config file?

# SPDX-FileCopyrightText: 2020 Efabless Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # SPDX-License-Identifier: Apache-2.0 set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" set script_dir [file dirname [file normalize [info script]]] set ::env(DESIGN_NAME) MBA_module set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/MBA_module.v" set ::env(DESIGN_IS_CORE) 0 set ::env(CLOCK_PORT) "clk" set ::env(CLOCK_NET) "counter.clk" set ::env(CLOCK_PERIOD) "10" set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 100 250" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(PL_BASIC_PLACEMENT) 1 set ::env(PL_TARGET_DENSITY) 0.4 # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper) # where the PDN is planned on metal 5. So, to avoid having shorts between routes # in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. # # set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} # You can draw more power domains if you need to set ::env(VDD_NETS) [list {vccd1}] set ::env(GND_NETS) [list {vssd1}] set ::env(DIODE_INSERTION_STRATEGY) 4 # If you're going to use multiple power domains, then disable cvc run. set ::env(RUN_CVC) 1

Do you get this error when you run

make MBA_module

from the

/home/mukul/Desktop/design1/jubilant-funicular

directory?

yes

It looks to me that your $script_dir variable should be set to

/home/mukul/Desktop/design1/jubilant-funicular/openlane/MBA_module

but instead it’s set to

/home/mukul/Desktop/design1/jubilant-funicular/openlane/MBA_module/runs/22_12_30_04_04

Not sure why that would happen unless the scripts have changed. Your config file is expanded to a similarly named config file in the

runs/22_12_30_04_04

directory. Can you open that file and check the definitions?

This file is from directory runs/22_12_30_04_04

The file in runs/22_12_30_04_04 should be automatically created. You can try deleting it and rerunning. Or maybe switch to

config.json

file.