We are wondering whether the bottom line should read inout [`MPRJ_IO_PADS-3:8] analog_io, instead?

I think that would be a good idea for a future Caravel upgrade (to avoid confusion).

You can't define vectors in verilog that don't go to zero. Yes, it's an annoying limitation of the syntax.

@Tim Edwards I would understand that a tool might have problems with it, but I'm not sure that it is a limitation by Verilog. I just looked up a (handy) case from 2003 where modelsim accepted wire [7:4] and just tried Xilinx with ouput [64:1] ... and both tools did\do not complain.

I don't remember what part of the flow failed, so it might not be the verilog syntax itself, but some tool's interpretation of verilog syntax. Regardless, I tried it, and I could not get it to work unless all my vectors ended in zero.

I think there is a OL parser which parses top level RTL and prepares a lot of files for the flow, before starting synthesis. I can't recall the case, but there have been other issues with it here on slack as well. I think that parser requires vectors downto 0. It would be worth a suggestion to OL to generate these files based on the synthesis result, because a netlist is easier to parse than an RTL file. But it would also mean some restructuring, I guess. Also for instance, when IOs are removed by synthesis (e.g. user_clock) then the files generated by the RTL parser don't match the synthesis result (netlist) anymore. Once you know it, then you can live with it, but if you are a newbe like myself its painful.

If anyone wants to track down where the syntax is being abused and get the tools fixed, I would be very happy to rewrite the caravel RTL to avoid the ridiculous expressions needed to deal with the index limitation.

Right, thats understandable. Thanks for clearing it up!