Hi @Tim Edwards - the auto-generated transistors in magic have a pitch of 0.48um between gates. However we seem to be able to do 0.44um or even 0.43um pitch without any DRC errors. Is there a reason why the auto-generated ones are so conservative?

Referring to which type of transistor in which process?

Sky130_fd_pr__nfet__01v8

I see what you mean, and honestly, I'm not sure. The geometry gets rather difficult to describe when the length or width is short and diffusions have to use "dogbone" geometry, and it is probably just an inefficiency in the equations somewhere that got missed.

Okay thank you! as long as its safe to do the .043um pitch, we are all good.

One thing about the auto-generated transistors, though: You can always edit them. If you ever try to change a parameter and regenerate the layout, your edits will be lost, but as long as you don't touch it, the layout will continue to have your edits.

That is good to know!

I just looked at the layouts. The way that magic draws the gates (separated) prevents it from getting the gates as close as 0.43um pitch. I definitely need an option to combine gates and just draw a single set of connected poly contacts across the top and/or bottom of the whole array of fingers, which make it easy to compress the pitch down to 0.43um.

Yes we did think ourselves that it would be brilliant if there was an option to generate transistors with connected poly contacts!

Well, if you ever feel like writing a lot of Tcl code. . .