open-source-silicon.dev

what does 'clock reconvergence pessimism' mean - all these things I have failed to google

<@U0172QZ342D> I had to google a little bit because I had some missing parts, but basically when doing the calculations for the data arrival and data required paths each uses a different `derate` multiplier, to make them a little bit slower or faster, to account for possible differences in the chip cells. Always in a pessimistic way (making data arrival slower for MAX sta and faster for MIN?)
But that pessimism doesn't make sense for the parts of the paths that they have in common, so the `clock reconvergence pessimism` just corrects that difference.
I don't have a small example, but I can show you how you can check with one example if you want.
The derate values are set in the SDC I think:
```set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
```
The two links I used to remember more about it:
<https://vlsi.pro/common-path-clock-reconvergence-pessimism-removal/|https://vlsi.pro/common-path-clock-reconvergence-pessimism-removal/>
<https://vlsi.pro/set_timing_derate/|https://vlsi.pro/set_timing_derate/>

In openlane there is a `SYNTH_TIMING_DERATE` config value that is probably used to generate the .sdc
```Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing.
(Default: +5%/-5%)```