@Tim Edwards @Mitch Bailey A general question about magic's extraction. If I have circuit's layout and I extract a spice netlist using magic without any parasitics. What parameters of devices changes in the extracted spice netlist as compared to it's cdl netlist.

@Pranav Lulu By cdl netlist, I assume that you mean the spice netlist output of xschem for LVS. The standard library “cdl” netlists are actually just extracted spice. xschem outputs

ad, as, pd, ps

as formulas based on

W, L, nf,

and

M

. However, magic extracts these as zero values. During LVS, the 4 area and perimeter values are ignored. I’m not sure what difference this will make between simulation of the xschem netlist with area and perimeter and simulation of the extracted netlist without area and perimeter. @Tim Edwards Is my explanation correct? @Stefan Schippers Any comments?

@Mitch Bailey: The general practice for LVS has been to run magic's extract command with the option

extract no all

, which (among other things) doesn't check diffusion areas and perimeters, which is why

ad

,

as

,

pd

, and

ps

end up zero. But yes, you don't normally try to check those values with LVS. There will be some difference in simulation due to the difference in parasitics, but that's why you normally simulate on a netlist extracted with parasitics and not on the netlist extracted for LVS (other than to confirm basic functionality).

@Tim Edwards So using

extract do all

will extract

ad

,

as

,

pd

, and

ps

?

@Mitch Bailey: Yes, although with varying degrees of accuracy. The default behavior when there are multiple transistor sources and/or drains connected to the same net is to dump all

ad

,

as

,

pd

, and

ps

onto a single device and leave the remaining ones zero. You can get a better result by using the

ext2spice -d

option, which distributes the values equally among all transistors connected to the same net. That's usually good enough that it isn't worth quibbling about the fact that magic doesn't really know what the individual contributions of each transistor are.

@Tim Edwards @Mitch Bailey Thanks!! So a correct cdl netlist should include as, as, pd and ps along with W, L, nf and M which can be the used for simulation as well as LVS. As Mitch said the as, as, pd and ps are ignored during LVS. Am I right?

That’s my understanding.

@Mitch Bailey @Pranav Lulu @Tim Edwards The approach I used when designing chips years back was to check the transistors with L, W, nf and m, and NOT checking as/ad/ps/pd/nrs/nrd values. For simulation purposes xschem calculates reasonable values for as, ad, ps, pd, nrs, nrd using W, L, nf, m and minimum layout drawing rules, this adds some reasonable parasitic capacitances, and is probably better than having unspecified values for spice accuracy. However a parasitic extraction from layout might return the exact drawn values for these areas/perimeters. You may want to annotate these values in your original schematic (or -better- replacing completely the schematic netlist with the layout parasitic netlist extraction for the whole circuit block) if you want more precise parasitic area/perimeter values. The most important thing by the way is that parasitic extracted netlists add the interconnection capacitances that are fundamental for timing / functional post layout verification of the circuit. Note that specifying some values for as/ad/ps/pd/nrs/nrd in a mos transistor in the schematic overrides the equation based calculation.