open-source-silicon.dev

You seem to have hand-placed the `clkbuf_4`  cells because the cells are too far apart to be abutting on their abutment boxes.  I expect that they might be vertically shifted by 5nm (one internal unit, or one manufacturing grid unit) which causes the 5nm local interconnect spacing errors.

I remember that I had zero DRC errors before, then I did something and suddenly I had over 800

<@U03QSBWN0TU> Did you solve this? I was thinking that maybe your cell has been duplicated and offset by 1 unit. Try selecting and deleting and then maybe replacing.

I talked with tim and we came to the conclusion that it was becuase I accidentally opened the file with the wrong tech (I didn't load the config file), and it snapped everything to the nearest 0.01 um instead of the 0.005um for the SKY130A process

what I did was I manually went back and replaced all the transistors to force magic to reload them, that worked and I was able to get rid of all the DRCs with a few hours of work