open-source-silicon.dev

cts_buffer.png

<@U018LA3KZCJ> I see CTS starting from the center of the Macro and building the clock tree. But it does not buffer from Pin to the first CTS cell. My Marco is 1500um x 200um. I see around 1000um distance between clock buffer and clock pin. At top-level timing analysis showing this is creating 700ps timing due to long transition. Is there is way to enable the clock tree buffer between clock pin to first CTS buffer?

repair_clock_nets should handle that.  Something is odd about your picture though as the 1st buffer is not in the middle of the block from what I can tell.  What is the instance name of the 1st buffer?

cts_node.png

Highlighted one is Antenna diode, immediate next one is clk-buf 16

next_cts_buf.png

cts_buf_enb.png

I see repair_clock_nets enables with non zero CTS_CLK_MAX_WIRE_LENGTH value.
repair_clock_nets -max_wire_length $::env(CTS_CLK_MAX_WIRE_LENGTH)
I tried with set ::env(CTS_CLK_MAX_WIRE_LENGTH) {250} and see there is buffer with-in 100um
But succeeding buffer looks to be normal buffer, instead of clock buffer ?

Its very hard to make out the problem from all these images.  Would you just open an issue with a test case?