Hadir Khan
12/23/2022, 1:33 AMHadir Khan
12/23/2022, 1:35 AM// Configure lower 8-IOs as user output
// Observe counter value in the testbench
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
//reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
//reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
//reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
The user_defines.v file changes:
`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_OUTPUT
The test is failing:
MPRJ-IO state = zzz01100
MPRJ-IO state = zzz01101
MPRJ-IO state = zzz01110
MPRJ-IO state = zzz01111
MPRJ-IO state = zzz10000
MPRJ-IO state = zzz10001
MPRJ-IO state = zzz10010
MPRJ-IO state = zzz10011
MPRJ-IO state = zzz10100
Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed
Pins 5-7 are zHadir Khan
12/23/2022, 1:35 AMTim Edwards
12/23/2022, 3:36 AMUSER_CONFIG_GPIO__XX__INIT
is only used in the RTL, where the module of gpio_defaults_block
can be parameterized. But the module is a hardened macro, so the gate-level netlist can't be parameterized. There has to be a separate netlist for each block that has a unique defaults setting. The script that applies the defaults creates new gate level netlists, one for each configuration, with names like gpio_defaults_block_1803
, with the hex name of the configuration code suffixed to the name. Without running that script, the gate level netlist has only gpio_defaults_block
(for everything except the first five GPIOs, which cannot have their defaults changed), and gpio_defaults_block
defaults to a configuration word of all zeros, which turns off both the input and output buffers and leaves the GPIO in a high-impedence state. So the GPIOs cannot be simulated in gate level netlist without first running the script (scripts/gen_gpio_defaults.py
).
All that being said, the C code you posted is another problem altogether. The configuration triggered with reg_mprj_xfer = 1
has nothing to do with the power-on defaults in user_defines.v
. By triggering the load, you are automatically overriding the power-on reset state with the configuration saved in the reg_mprj_io__XX_
registers. Because you commented out those lines, the registers take their default values, which are in the housekeeping module, not in user_defines.v
. Ideally they should be the same, but the two sets of values are held in places far away from each other (one near the pin, the other in the housekeeping module). So they remain two independent sets of values. The housekeeping module defines the default value to be a management-controlled input (see housekeeping.v
line 1094 in the sky130 version of caravel), so if you don't set the register values in your C code, that's what they will be.
The underlying rule here is that you either (1) use the default values from user_defines.v
and don't trigger the configuration serial load, or (2) you set all the register values to the configurations you want, and then trigger the configuration serial load.Sud_ana
12/23/2022, 8:54 PMHadir Khan
12/24/2022, 7:22 AM`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_OUTPUT
The C file is just
#include <defs.h>
#include <stub.c>
void main()
{
reg_spi_enable = 1;
}
Our design is correctly producing output on io[11] as shown in the waveform below but the caravel io pad [11] remains z
any ideas?Tim Edwards
12/24/2022, 5:59 PMgpio_defaults_block_1808
and the gate level netlist for caravel is instantiating it for GPIO 11, and your project holds the OEB pin low on the pad interface and drives the output low, then it should work in simulation.Hadir Khan
12/25/2022, 9:23 AM