so there should be 5

You have a power - ground short somewhere. Check your extract messages - it might tell you which circuit.

I verified there is no such short

there is a short over substrate

where?

nfet substrate connection is to power while the xres bulk connection is to ground. You’re also missing nwell taps for your standard cells.

oh I see my issue

There is a

sky130_fd_sc_hd__tapvpwrvgnd_1

cell that has connections to well and substrate that should be included in every standard cell placement (and repeated if the cell row is long).

how do I add this cell

I’m not that familiar with magic, but I assume it’s just like adding the other standard cells in the design (or did you use

Import spice

?

i used import spice

You could add it to the spice file manually. But looks like in magic, 1. select the lower left point 2. Cell->Place instance 3. Select

sky130_fd_sc_hd__tapvpwrvgnd_1.mag

from

$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/mag

cool

You need at least 1 in each horizontal group of standard cells. Openlane places one about every 25um in a row of standard cells.

image.png

The wells need to touch. You can add fill cells or decap cells to connect all the wells horizontally.

image.png

Technically, everything is connected correctly and LVS should pass, but from a physical layout standpoint, well resistance is much higher than metal or diffusion. Since your design is not that large, you may be ok, but I’d recommend adding tap cells at least on the right side also. You’ve drawn PWEL, but actually this layer is ignored. Everything not NWEL is physically PWEL.