I’m finally getting around to adding tests to my s...
# sky130t
Tholin
12/19/2022, 10:21 PMI’m finally getting around to adding tests to my submission, but I am immediately encountering issues just reading the outputs from my design. I opened the results of the latest run in GTKWave here. Top is the clock, middle is what my design is generating on io_out, bottom is what appears on the mprj_io output I can check in the testbench Verilog file. Output enables are set correctly. SPI flash firmware is correct. Nothing should be stopping this from working, yet it does not. I spent all day trying everything I could think of, and nothing I do changes the result ever, so any help appreciated, thanks.
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Mitch Bailey
12/20/2022, 1:03 AMCan you provide a link to your repo?
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Tholin
12/20/2022, 9:48 AMTholin
12/20/2022, 9:49 AMI found a temporary workaround to allow me to access io_out on my wrapped design from the testbench, but I’d still like to know that the outputs I want will appear on the actual I/O pins.
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Mitch Bailey
12/20/2022, 10:29 AMWhat are your gpio settings in
verilog/rtl/user_defines.vt
Tholin
12/20/2022, 11:24 AMAll of them except io’s 9:5 (which are inputs) are outputs. The defines in the repo are up to date.
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Mitch Bailey
12/20/2022, 1:11 PM@mshalan who’s responsible for the verilog testbenches?
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Matt Venn
12/20/2022, 4:12 PMuser_defines.v doesn't make any difference at simulation stage
Matt Venn
12/20/2022, 4:15 PMMatt Venn
12/20/2022, 4:15 PMyou probably want user output not mgmt output
Matt Venn
12/20/2022, 4:15 PMif you want your design to control the ios
Matt Venn
12/20/2022, 4:15 PMMatt Venn
12/20/2022, 4:17 PMGPIO_MODE_USER_STD_OUTPUT
Matt Venn
12/20/2022, 4:17 PMis what you want
Matt Venn
12/20/2022, 4:18 PMplus your io_oeb driven low for all pins you want to be outputs
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Tholin
12/20/2022, 4:45 PMOh, that's such a silly mistake. I see now. Thank you.
Tholin
12/20/2022, 4:46 PMI did not know there is a difference