Hi , In Yosys is there any way to bit blast the nets/ports while writing verilog ? I.e convert the busses from [0] to 0 Thanks

splitnets will do bitblasing in general: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/splitnets.html for your case I think you would want to pass

-format __

or similar, otherwise you'll end up with single bit nets called

foo[0]

,

foo[1]

, etc

yup... tried that...works.. thnx