#1568 Provide a Spice model of final circuit that includes parasitics Issue created by growly Description It seems useful to provide a Spice model that includes extracted parasitics at the end of the flow. Proprietary tools readily make this available, and it makes sense to provide the parasitics in a format readily available for the user's simulations. Proposal I don't know if existing tools in the flow can do this, but BigSpicy can. It can merge Verilog, Spice and SPEF netlists. It can also do things like • extract capacitively-coupled networks • extract paths between given input/output nodes • flatten the design to the transistor level (for analog designers) It can easily be run as a (possibly optional) step in the flow to dump the merged Spice view for the user. Ideally we wouldn't have to export to SPEF and Spice and then re-merge them, but absent another option this does work. The-OpenROAD-Project/OpenLane