what is the issue

You will need to post the other LVS report. The log file above is just the terminal output of netgen and is not the full LVS report.

@Neha Maheshwari From similar results, it looks like you may have tie cells at the top level that aren’t being placed in standard cell rows with tap connections. Often, top level is not synthesized - only routed. You could try tying your inputs inside

arbiter_puf

rather than at the top level.

inside instantiation