Hi @jeffdi I wanted to ask is there any way to limit the useage of memory during thr FEOL stage of pre-checks as my designs are failing this stage and after inspecting the logs I am certain this is due to running out of memory. I am facing same issue on my local machine as well. Does this have to do with the size of the project? This kind of issue is making designing very dufficult on systems which are not very high end.

Hi we were discussing the same in this thread. https://open-source-silicon.slack.com/archives/C03R1GRP9LG/p1670088642030629