(unrelated to my previous question) I have a desig...
# openlane
a
(unrelated to my previous question) I have a design that hangs openlane during synthesis. it doesn't crash, it pegs one CPU at 100% for at least 7 hours before i get tired of waiting and kill it. the log output stops growing mid-line. where can i file this bug?
ah, i see that the issue moves with openlane to the-openroad-project
v
Which
SYNTH_STRATEGY
is used?
a
possibly i am running into the same issue as this: https://github.com/The-OpenROAD-Project/OpenLane/issues/1514
it was default but i'm trying 'DELAY 0' now
v
Try
DELAY 4
if facing issues with
DELAY 0
🙏 1