open-source-silicon.dev

IMG_20221205_165031.jpg

<@U016HSAA3RQ> Here, Screenshot is attached please check

<@U03L6FGLHV1> These look like actual DRC rule violations. See <https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html#lvpwell>

I am confused, why this is happening <@U017X0NM2E7>

If each and everything is done by tool. There should not be any specific drc violation

IMG_20221205_191524.jpg

<@U017X0NM2E7> if you look close there is no drc violation in my design than why in paycheck ?

I  don’t think the tools and pdk are mature. Can you look at the error result gds to see where the errors are?

<@U017X0NM2E7> Recently, I did three tapeout on sky130 PDK. I did not face any error like that

Different  process, different rules. Can you visually verify the errors?