Hi, I'm having XOR fail in precheck, can anyone gu...
# gf180mcu
c
Hi, I'm having XOR fail in precheck, can anyone guess why?
I'm starting to think it's the IO area.
m
What layers?
c
I don't know, I just looked at user_project_wrapper.xor.gds in klayout. Hope this is helpful.
m
Can you load that on top of your design in klayout?
c
Is it like this? There is certainly something growing there that I don't understand.
m
Right. Thereโ€™s a golden version of the wrapper that has the port positions for the connections to caravel. The XOR check makes sure everythingโ€™s in the right place.
c
So something is wrong at the
make user_project_wrapper
stage. I'm stumped....
golden version of the wrapper is wrong?
m
Either that or the pin positions in the config file. You could try opening the caravel gds and see where the actual pins should go.
j
@Mitch Bailey, I get the exact same issue! At metal layer 2 and Metal 3 I see the XOR differences. Attaching the reference image.
c
I'm not sure of the conditions, but it seems that some designs have different pin placements, which causes the precheck XOR to fail. user_proj_example did not have this problem, even though I changed the die size. I think that most of the designs currently submitted will not pass the XOR precheck.
j
I agree, my user_proj_example doesn't have the issue either!
r
Is this failing in the efabless submit stage or the pre-check on github?
c
It is failing in the efabless submit stage and local precheck.
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r
So, this may or may not be helpful, but it appears that the caravel_user_project repo is currently failing its tests (https://github.com/efabless/caravel_user_project). It seems that some people have forked (or cloned) that one.
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j
@jeffdi, @Matt Venn, is this an issue with Caravel_user_project? What could be the best solution?
m
FWIW, the XOR check is only on
user_project_wrapper
and
user_analog_project_wrapper
.
user_proj_example
is unaffected.
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v
@Cra2yPierr0t can you share your repo?
c
p
@Cra2yPierr0t I think you may have a problem with your power pins: power pin ใŒๅˆใ‚ใชใ„ๆฐ—ใŒใ™ใ‚‹ https://github.com/cpu-dev/caravel_jacaranda-8_GF180/blob/main/openlane/computer/config.json#L17-L18 https://github.com/cpu-dev/caravel_jacaranda-8_GF180/blob/main/verilog/rtl/jacaranda-8/computer.v#L19-L20
v
@proppy Good catch. Its good to move power pins inside respective PDK_FAMILY will be permanent fix. new user will not check those pins until they understand the flow.
c
@proppy If both config.json and config.tcl are present, config.tcl is used, so power pin does not seem to be the cause. https://github.com/cpu-dev/caravel_jacaranda-8_GF180/blob/main/openlane/computer/config.tcl#L73-L74
p
ah sorry!
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it would be best to remove the json file then ๐Ÿ˜›
j
@Cra2yPierr0t I posted a reply to the issue - your project looks like it is based on gfmpw-0a. You need to patch more files to get to gfmpw-0d. Your user_project_wrapper is out of date. See the patches in the release notesโ€ฆ https://github.com/efabless/caravel_user_project/releases/tag/gfmpw-0d
c
@jeffdi Wow! Thanks for the answer! I'll fix it and give it a try!
p
let me know if it fixes it.
c
@proppy Merged!! I'll get back to you shortly! Thank you๐Ÿ‘๐Ÿ‘๐Ÿ‘๐Ÿ‘๐Ÿ‘
@jeffdi @proppy XOR precheck passed! Thank you again for your cooperation.๐Ÿ‘
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