1. Executing Verilog-2005 frontend: /home/runner/w...
# gf180mcu
r
2. Executing Verilog-2005 frontend: /home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project/../../verilog/rtl/top.v 92 /home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project/../../verilog/rtl/top.v19 ERROR: Identifier `\xnor_y' is implicitly declared and `default_nettype is set to none. 93 Error: : during executing yosys script /openlane/scripts/yosys/synth.tcl 94 Error: : Log: ../home/runner/work/tiny_user_project/tiny_user_project/openlane/tiny_user_project/runs/22_12_04_08_00/logs/synthesis/1-synthesis.log 95 Error: : Last 10 lines: 96 child process exited abnormally 97 98 Error: : Creating issue reproducible... 99