Also, I'm trying to make sense of NP.5b DRC violat...
# gf180mcu
u
Also, I'm trying to make sense of NP.5b DRC violation:
NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm
What does it mean?
t
There have been some issues with klayout rules involving LVPWELL because some rules were written without the awareness that LVPWELL may be used outside deep-nwell, essentially as a marker layer for p-substrate, and also optional (lack of LVPWELL also indicates the p-substrate). The rule NP.5b indicates that NP (the N+ implant) must surround n-diffusion (COMP not in an n-well) by 0.16um.
u
Thanks! When I create my own transistors with magic, it seems to violate this rule. Is there anything I can do about it other than editing the files with klayout to fix COMP?
I can see magic generates 0.1 spacing between COMP and Nplus:
image.png
t
I am seeing 0.02um, but regardless, it is definitely an error, and I will get it fixed. Thanks for catching it.
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u
Thank you!
I ended up writing a klayout script that fixes it as a temporary workaround:
t
I'm puzzled by how my POR circuit passed DRC for the test chip we did last year, and I think it is still passing DRC, so this definitely requires some investigation. . .
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