How signal of .lef analog design will be connect w...
# analog-designf
Filippo
12/01/2022, 7:26 AMHow signal of .lef analog design will be connect with digital part in caramel during routing? With signals of the same name?
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Arman Avetisyan
12/01/2022, 7:33 AMcaravel or caravel analog?
Analog requires a final gds + spice and does not define the flow.
Caravel non analog cant route analog signals AFAIK. Maybe there is a way to configure openlane to do it, but there was issues in the past.
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Filippo
12/01/2022, 7:34 AMI mean when we use analog block in caravel digital project including it with led file
Filippo
12/01/2022, 7:35 AMFor example in a mixed signal project
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Arman Avetisyan
12/01/2022, 7:37 AMI just designed my analog cell in a way that when it is placed it will automatically connect to analog IO and I avoided any analog signals between analog cells.
Arman Avetisyan
12/01/2022, 7:38 AMBut in the past openlane used to insert buffers. Now you can configure it to remove the buffers.
Arman Avetisyan
12/01/2022, 7:38 AMOptionally you can add a LEF file with custom NDR and use OpenLane interactive to apply this non default routing rule
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Filippo
12/01/2022, 7:39 AMI mean if I want to connect the output of an analog cell (ADC) with the input of a digital one. ( a filter)
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Arman Avetisyan
12/01/2022, 7:41 AMoutput of ADC is digital signal. Analog signal is usually the IO. OpenLane routes the digital signals properly. Unfortunately you need .lib for proper timing fixing
Arman Avetisyan
12/01/2022, 7:44 AMAnd for analog signals see two messages above
Arman Avetisyan
12/01/2022, 7:47 AMThe flow will look like this:
1. Design the analog cells
2. Make lef
Optionally: Make .lib OR check timings manually
3. Use OpenLane to place and route the cell
3.1 Add analog nets to "remove buffer" list
3.2 Add NDR to analog signals to make it thick and low resistance
3.3 Make sure power/ground is connected using proper configuration
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Filippo
12/01/2022, 7:52 AMOkay perfect, in step 3 how openlane P&R the output of analog cell with for example input of a digital one? I need to connect in the verilog file instantiated the analog component ?
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Arman Avetisyan
12/01/2022, 7:55 AM3.1 and 3.2 is the only thing different for analog.
The rest I wrote here: https://openlane.readthedocs.io/en/latest/tutorials/index.html
For analog unbuffering see this: RSZ_DONT_TOUCH_RX
Arman Avetisyan
12/01/2022, 7:55 AMYou need the verilog blackbox of the analog cells
Arman Avetisyan
12/01/2022, 7:56 AMf
Filippo
12/01/2022, 7:57 AMThank you very much, very useful!
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