open-source-silicon.dev

CI_error_screenshot.png

I have a similar problem with re-submission of MPW7.  In order to run new timing analysis, the Makefile re-installed new versions of OpenLane.  I then completed mpw_precheck and tapeout and everything succeeded.  However, the CI scripts ran a day later and throws errors that the version of OpenLane installed does not match the one tested, and suggested a "make pdk".  I am halfway through this, but then realized that this new OpenLane install will probably force me to rebuild my project all over again.  Does this make my project now look like a new project and thus does not meet the terms of original submission date, and thus miss the lottery for MPW7 acceptance?  What should I do now?  It does seem that the CI script is doing the test on user_proj_example, not my project, so do I just update OpenLane and not re-run my project  (this will get past the error, but it does seem like a silly rule to get around for timing re-submission testing)?

Important thing is updating `user_defines.v` and running `make caravel-sta` and confirm that there is no violation for existing submission.
If there is violations you can fix by re-harden with latest OpenLane and submit it. Hope this help you to understand well.

I'm also seeing problems with CI failing  with mismatched pdk &amp; openlane

As <@U0268926L04> says, you need to check top level timing and fix the user_defines.

you don't need to reharden unless necessary to fix any timing violations

and as long as you keep the same efabless project, you won't lose your slot for mpw7

Yes, I have updated `user_defines.v` and ran `make caravel-sta`  There are some timing violations but they are all Max violations of the form:  SOC to external flash interface (flash_csb, flash_clk, flash_io0), soc/_30758_ (another ff clocked by clk) and also many timing paths to soc.core.RAM128 and soc.core.RAM256.  No other timing violations to user_project_wrapper code is found.  This happens for s-ck-max.rpt, s-max.rpt, and s-soc-max.rpt (only these files) in all nom, min and max
corners.  This was reported in <#C02K4RD241Y|timing-closure>.  There was a reply stating that these can be safely ignored.  I am working on whether I can make all of them go away.  In the meantime, I ran mpw_precheck and tapeout.  Both were successful.  The next day the CI runs complained regarding mismatched pdk and openlane.  I have not re-hardened so this mismatch is expected.  Should I still do a make pdk and upgrade openlane just to make this error message go away?  It seems to be checking user_proj_example to determine this, and should have no bearing on my project (as it has not been re-hardened using a later version of openlane)