Slot-009 of mpw4 has 13 single tristate outputs into inverters (found with CVC-RV). When the tristate output is Hi-Z, the inverter may have current through both the pmos and nmos and have indeterminate output. Maybe these outputs got buffered by mistake?

io_out[12]
io_out[15]
io_out[16]
io_out[19]
wbs_dat_o[0:7]
wbs_dat_o[15]

Here's a snippet from the gl verilog.

sky130_fd_sc_hd__dfxtp_1 _822_ (.D(_108_),
    .Q(net239),
    .CLK(\clknet_3_0__leaf_counter.clk ),
 sky130_fd_sc_hd__clkbuf_2 output239 (.A(net239),
    .X(wbs_dat_o[6]),

If the

dfxtp

is always enabled, no problem.

Not sure why a user output would be tristated---sounds like a misunderstanding of how the outputs operate in bidirectional mode. However, for one, the

io_out

signals from the user (and all signals from the user area back to the management SoC, including

wbs_dat_o

) are supposed to be applied to a NAND gate input, not a buffer, and the buffer was incorrectly added to the input of the

gpio_control_block

module (I created a github issue for it in the caravel repository). The buffers have been removed but that change is awaiting top level rerouting and has not been pushed to the repository yet.

May have something to do with synthesis. Here's the original rtl

assign wbs_dat_o[14]    = (la_data_in[32]) ? 1'bz : 1'b1;
    assign wbs_dat_o[15]    = (la_data_in[32]) ? 1'bz : tx_fifo_rd_start;
    assign wbs_dat_o[6]     = (la_data_in[32]) ? 1'bz : tx_fifo_r_data[6];
    assign wbs_dat_o[7]     = (la_data_in[32]) ? 1'bz : tx_fifo_r_data[7];
    assign wbs_dat_o[5:0]   = (la_data_in[32]) ? 6'bz : tx_fifo_r_data[5:0];
    assign wbs_dat_o[31:16] = 0;
    assign wbs_dat_o[13:8]  = 0;

    assign io_out[12]       = (la_data_in[32]) ? o_ready : 1'bz;
    assign io_out[17]       = (la_data_in[32]) ? o_valid : 1'bz;
    assign io_out[15]       = (la_data_in[32]) ? o_bof : 1'bz;
    assign io_out[16]       = (la_data_in[32]) ? o_eof : 1'bz;
    assign io_out[24:19]    = (la_data_in[32]) ? o_data : 6'bz;
    assign io_out[31]       = (la_data_in[32]) ? ~wb_clk_i : 1'bz;

I'm no expert and I haven't checked the gl verilog, but looks like a conditional assignment. This could be implemented with 2 tristate outputs with

la_data_in[32]

as the selector. There may be a problem where half gets optimized out. I'll explain it to the designer when they get back to me.

That appears to be a misunderstanding of the way the wishbone bus works. The user project should simply output to `wbs_dat_o`; the wishbone master will read the data conditionally upone the address being in the user project. Likewise, the io_out is only seen if the GPIO is in output mode, so there is no need to tristate

io_out

. Since the

wbs_dat_o

is tristated on one value of

la_data_in[32]

and

io_out

is tristated on the other value, then there's always something that's incorrectly set.