@Tim Edwards While running soft connection checks on the mpw-5 designs, I noticed that slot-026, a hand drawn flash layout, has an unconnected dnwell that I don't believe will be detected in LVS/DRC/CVC. Is it possible to extract parasitic well diodes (psub-nwell, pwell-dnwell, psub-dnwell) in magic and then ignore those during LVS? If that's possible, CVC would be able to detect bad connections.

True. Processes that have specific models for devices in deep wells have 5- and 6- pin devices that include the pwell, deep n-well, and substrate, and model all of the diodes within the model. But with only 4-terminal device models, you can't really. I have not thought through what would be needed to extract parasitic diodes. It is not currently possible but it shouldn't be particularly hard to implement. Magic can recognize the parasitic cap between pwell and deep nwell and between deep nwell and substrate. If it can identify the parasitic capacitor (and measure the area of it), then it can also identify an associated parasitic diode.

Looking at http://opencircuitdesign.com/magic/techref/maint2.html pwell-dnwell diodes may be extractable with

device diode

with pwell over dnwell as the recognition layer and nwell guardring as the cathode. psub-dnwell diodes may be extractable with

device subcircuit

which allows no terminal devices. dnwell would be the recognition layer and the substrate would be the other. The order would have to be reversed for verification though. psub-nwell diodes could be extracted the same as above.

Yes, but the trick here is to make them parasitic, which is to say that there needs to be a way to distinguish between marked diode devices that are intended for LVS and parasitic devices that get handled by a full extraction; then there needs to be a way in ext2spice like "cthresh" to control when diodes are output. And then maybe an option to turn it of during initial extraction, since analyzing every well in the design could create a serious performance issue for extraction (maybe not, but it needs to be considered). Finally, you can't just blanket extract a diode for every nwell, since most device models will already include the diode. So normally you wouldn't extract parasitic diodes for LVS, but then once again the problem would not be caught by LVS. I think the real solution is that where there is a deep nwell, there should be 5- and 6- terminal device models.