<@U039DRK4BFY> we are now seeing this in the final...
# chipignite
c
@Nathan Pier we are now seeing this in the final tapeout check:
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STDOUT: {{Step Update}} Executing Check 4 of 5: Klayout Metal Minimum Clear Area Density on [caravel_22064452.oas]
STDERR: [ WARN ] MET Density Check Result: 'caravel_22064452.oas' has 1 DRC violations.
not sure what to do about it though?
n
@mkk @jeffdi I'm adding some of our team to this thread so they can provide technical support.
c
ok. we are trying a different version that has one more block ...
j
j
met densities are specified as clear area which must range from .4 to .65 for li, m1-4. met 5 must range from .24 to .55
typically issues with being under on Li are due to using too many or all fill cells in a design vs decap. too high Li is usually due to using decap only. One solution is to use the modified EF decap size 12 cell which has a balanced Li and diffusion. This will address issues with Li density as well as FOM density (tap+diffusion). FOM density is specified using 700 um tiles stepped at 70um and must range between 0.38 and 0.57 (not clear area).
if you are using OpenLane, you can adjust your config.tcl to use the modified decap cell.
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set ::env(DECAP_CELL) "\
	sky130_fd_sc_hd__decap_3 \
	sky130_fd_sc_hd__decap_4 \
	sky130_fd_sc_hd__decap_6 \
	sky130_fd_sc_hd__decap_8 \
	sky130_ef_sc_hd__decap_12"
@Jasper van Woudenberg @Christopher Batten ^^
c
we just barely met the 0.4 limit when we submitted an updated version of our chip ... whew. For the future, can we put the DECAP_CELL command in our projects config.tcl? or do we need to do that in the PDK?
j
you can include in the config.tcl
thats great