Do anyone here has experience with nMOS well isolation? I was talking to a colleague of mine the other day and they asked about whether or not I intended to use deep Nwell isolation in my circuits, and I didn't know what to answer.

I unsed nMOS well isolation for a difference amplifier, so the bulk and source could follow the gate and the operating point would not shift with the common mode voltage.

I have used it to create isolation between circuits. It allows you to separate ground connections (say between a low-jitter clock gen circuit and a bank of comparators with signal dependent switching) without having a conductive short through the substrate. The effectiveness at high frequencies is limited by your ability to create low-impedance ground connections off chip for the two circuits. At very high frequencies, you'll have capacitve coupling between the two grounds through the DNW/SUB diode capacitances. Feel free to message me if you want to discuss further.

Yes, I have been using triple-well many times to isolate the NMOS from the substrate.

Hello, I have a question regarding this: Is it possible to use isolated devices for the 10.5v flavor? How can i check this?

Principally any NMOS can be put into the pwell that sits in the nwell in the p-substrate. The question is whether the PDK supports this for all devices. Take a look at the devices in question in the layout and compare layers, and check if there either is a model available or you can hack one (by adding the extra diodes by hand).