open-source-silicon.dev

Hello,
I am trying to know whether xschem can synthesize Verilog or not?
Thanks

xschem is a schematic drawing and schematic capture tool, so no, it does not synthesize Verilog.  Openlane is the tool that synthesizes verilog (specifically, Yosys is the tool and Openlane is a set of wrapper scripts around Yosys and OpenROAD).

<@U03EC4ED53J> Although xschem can not synthesize gate level verilog from rtl, it can output a schematic in verilog format.

Did you mean that xschem can read in synthesized Verilog? In essence, does Yosys create a synthesized Verilog file that I can then import into xschem?

That is not what I meant. I meant that if you create a schematic in xschem, you can output that in verilog format.
I haven't found a direct verilog to xschem `sch` conversion.
However, there is a spice to sch conversion process here. <https://github.com/StefanSchippers/xschem_sky130/blob/main/decred_hash_macro/README.md>
<@U016EM8L91B> says that you can use qflow to convert verilog to spice, so you could probably script something, but I don't know how useful the results would be.