<@U025YC3GX9R> With latest OpenLane flow getting L...
# lvsv
Vijayan Krishnan
07/25/2022, 1:42 PM@Dinesh A With latest OpenLane flow getting LVS mismatch.
Copy code
core0_debug[37] |core0_debug[45] **Mismatch**
core0_debug[45] |core0_debug[37] **Mismatch**d
Dinesh A
07/25/2022, 3:29 PMSince there was no change in this Macro, I have not re-harden with latest tool set. Let me cross-check.
If feel this is LVS tool OR OpenRoad Tool issue ? Tool is picking the Golden RTL and doing all the process to generate GDS. It should have generated a LVS clean database.
Dinesh A
07/25/2022, 3:50 PMWhen I run the ycr_iconnect with mpw7 tool set, i see LVS error different pins. When updated the ycr_iconnect/config.tcl
From:
set ::env(CELL_PAD) "14"
to
set ::env(CELL_PAD) "2"
set ::env(GLB_RT_ADJUSTMENT) {0.2}
I don't see any LVS error ...
Can you cross-check from your end ? I also pushed only this config.tcl to github
v
Vijayan Krishnan
07/26/2022, 6:38 AMI've updated and still see the same error with OpenROAD: 475ff5e827b8937f4810ecae75973ee74e457816 and latest OpenLane
Vijayan Krishnan
07/26/2022, 6:39 AMdifferent net
Copy code
core_irq_lines_i[8] |core0_debug[21] **Mismatch**
core0_debug[21] |core_irq_lines_i[8] **Mismatch**Vijayan Krishnan
07/26/2022, 7:03 AM2022.07.23 this tag throws LVS error, but 2022.07.26 tag there is no LVS error
d
Dinesh A
07/26/2022, 7:17 AMI see this issue related is more towards Tool .. You need to see what are changes between two tag. I have not done any design changes in this block post MPW-6
v
Vijayan Krishnan
07/26/2022, 7:19 AMok. I'll look into that
3 Views