Hello guys, I am trying to run a ring oscillator through openlane and it keeps simplifying my design, is there a way to tell it to not simplfy the design?

Try: (* keep *) reg chain[20];

Thanks

Also, instantiating the inverters standard cells explicitly works, yosys doesn't optimise them out.

Thanks, that is what I ended up doing and was able to get a proper gds file to output.

This may help: https://github.com/mattvenn/instrumented_adder

Thank you, I will take a look at that.